Concept of Image Processing Based Architecture

Now a days microcomputers to general purpose large computers are used in image processing. Dedicated image processing systems connected to host computers are very popular. Special coprocessor card and parallel processor are also being included in many small systems to gain speed. Interactive graphic devices are also added to provide image editing facilities. Digitized image arrays are in most cases very large. So, sufficiently large core memory should be provided with the system. These working systems should have adequate and efficient secondary large storage facility. Here, magnetic tapes and disks are the most popularly used storage media. Image processing programs are often coded in assembly language for fast execution, the flexibility of the system can be improved by having high-level languages for use in the development phase. Depending on the requirement various image processing architectures are designed and are available in the market. For example machines for scientific research are different from commercial ones, as to solve a particular problem may need a special architecture. On the other hand in industrial application, a machine needs to do particular job in real time. Accordingly four major distinctions of it are made:

1         Scientific research and commercial machines

2         Real time and off-line machine

3         Machines for imaging and machine vision job

4         Machine for process control and inspection

Most of the image processing hardware is based on one of the following architectural concepts:

i)                    Serial or von Neumann architecture : It is a low- cost traditional serial processor based on a microprocessor chip with a complex instruction set (CISC) or reduced instruction set (RISC)

ii)                   Multiple – instruction multiple-device microprocessors: It is small array of RISC or CISC elements and is characterized by interconnections among processors as well as interconnections between processors and memory element.

iii)                 Pipelines: It is also an MIMD architecture where identical processors are connected in a sequence. Algorithm is decomposed and mapped to this sequence such that each processor executes only sub-task in order. So image data go in at one end at frame rate, passes from one programmable module to the next, and finally resultant image comes out of another end at the same rate.

iv)                 Single instruction multiple device (SMID) parallel processors: It usually operates on image bit-planes in parallel. In that case, it is called single-bit SIMD. However, it may be designed to operate on the whole byte or a complete word also. 

Contributed by: Biswajit HalBiswajit Halder