Tasks Scheduling Algorithm for Multiple Processors with Dynamic Reassignment

Distributed computing systems [DCSs] offer the potential for improved performance and resource sharing. To make the best use of the computational power available, it is essential to assign the tasks dynamically to that processor whose characteristics are most appropriate for the execution of the tasks in distributed processing system. We have developed a mathematical model for allocating “M” tasks of distributed program to “N” multiple processors (M>N) that minimizes the total cost of the program. Relocating the tasks from one processor to another at certain points during the course of execution of the program that contributes to the total cost of the running program has been taken into account. Phasewise execution cost [EC], intertask communication cost [ITCT], residence cost [RC] of each task on different processors, and relocation cost [REC] for each task have been considered while preparing a dynamic tasks allocation model. The present model is suitable for arbitrary number of phases and processors with random program structure.

Consider a distributed program consisting of a set T={t₁,t₂,t₃,..,t_M} of M tasks to be allocated to a set P={p₁,p₂,p₃,…,p_N} of N processors divided into K phases. The basis for dynamic program model is the concept of the phases of a task program. With each phase the following information is associated:

(1)The executing task during this phase and its execution cost on each processor in a heterogeneous system.

(2)Residence costs of the remaining tasks, except for the executing task, on each processor. These costs may come from the use of storages.

(3)Intertask communication cost between the executing task and all other tasks if they are on different processors.

(4)An amount of relocation cost for reassigning each task from one processor to the others at the end of the phases.

In general, the objective of task assignment is to minimize the completion cost of a distributed program by properly mapping the tasks to the processors. The cost of an assignment A, TCOST(A), is the sum of execution, intertask communication, residence, and relocation costs.

   Contributed By:    ARUP ROY,  LECTURER (CSE)  , MALLABHUM INSTITUTE OF TECHNOLOGY.            

Microprocessors Operating at below 1 volt!!

TI's MSP 430 family, we already know, is one of the lowest power consuming micro family. Now comes news of a new device that takes this to new lows! MSP430L092 operates at below 1 volt, at 0.9 v precisely. What's more remarkable is that all the analog and digital parts work at this voltage, there are no voltage boosting circuitry on chip.


The new member can work at 0.9 to 1.65 v range. The core is a 16 bit RISC working at 4 MHz and the power consumption is just 45 microA/MHz!!!! 2KB RAM and 2 KB ROM make up the memory system.  There are several timer peripherals, such as the 32-bit Watchdog timer and two 16-bit general purpose timers. This device has  11 I/Os that are also interrupt capable. There's a  Analog Pool IP has several new features.The Analog Pool, or APOOL has basic blocks such as a 256mV voltage reference, a Comparator, and an 8-bit DAC. 


Like other members of the family this too is well suited to create a highly portable instrument that lasts and lasts on batteries.

Concept of Image Processing Based Architecture

Now a days microcomputers to general purpose large computers are used in image processing. Dedicated image processing systems connected to host computers are very popular. Special coprocessor card and parallel processor are also being included in many small systems to gain speed. Interactive graphic devices are also added to provide image editing facilities. Digitized image arrays are in most cases very large. So, sufficiently large core memory should be provided with the system. These working systems should have adequate and efficient secondary large storage facility. Here, magnetic tapes and disks are the most popularly used storage media. Image processing programs are often coded in assembly language for fast execution, the flexibility of the system can be improved by having high-level languages for use in the development phase. Depending on the requirement various image processing architectures are designed and are available in the market. For example machines for scientific research are different from commercial ones, as to solve a particular problem may need a special architecture. On the other hand in industrial application, a machine needs to do particular job in real time. Accordingly four major distinctions of it are made:

1         Scientific research and commercial machines

2         Real time and off-line machine

3         Machines for imaging and machine vision job

4         Machine for process control and inspection

Most of the image processing hardware is based on one of the following architectural concepts:

i)                    Serial or von Neumann architecture : It is a low- cost traditional serial processor based on a microprocessor chip with a complex instruction set (CISC) or reduced instruction set (RISC)

ii)                   Multiple – instruction multiple-device microprocessors: It is small array of RISC or CISC elements and is characterized by interconnections among processors as well as interconnections between processors and memory element.

iii)                 Pipelines: It is also an MIMD architecture where identical processors are connected in a sequence. Algorithm is decomposed and mapped to this sequence such that each processor executes only sub-task in order. So image data go in at one end at frame rate, passes from one programmable module to the next, and finally resultant image comes out of another end at the same rate.

iv)                 Single instruction multiple device (SMID) parallel processors: It usually operates on image bit-planes in parallel. In that case, it is called single-bit SIMD. However, it may be designed to operate on the whole byte or a complete word also. 

Contributed by: Biswajit HalBiswajit Halder

Jolicloud -Lightweight OS for Netbooks

             

               Netbooks are not like a fully powered Notebook and thus working with Windows on Netbooks could be irritating at times. There is a very light weight operating system designed specifically for the netbooks, called Jolicloud. We all know that Windows Vista didn't work well even on fulls-cale notebooks. One of the reasons most of the Netbooks comes with either Windows XP or some platform of Linux. It is quite slow for the low-powered netbooks alright.

Jolicloud may remind us of the smartphones because, it is application-centric. It comes with many applications already installed, like Facebook, Google Reader (must for bloggers), Times Skimmer, Google Docs, Gmail and even DropBox etc. If we want, we can also add any supported application in the blink of an eye.

 The architecture of Jolicloud consists of mainly three components. One is the kernel, next is the user interface which is quite an impressive one and finally the Jolicloud homebase. This homebase is actually free from the netbook and it helps one in linking up the notebooks together. It means, any update on your one netbook will automatically be made available in other linked netbooks.Jolicloud is based on GNU/Linux, Kernel.org, Ubuntu and Debian that has been optimized and extended for netbooks.

GMA 500 support was not optimal in Linux OS. The driver is developed by Tungsten Graphics, not by Intel, and the graphic core is not an Intel one, but is licensed from PowerVR. This led to an uncertain mix of open and closed source 3D accelerated drivers, instability and lack of support. Ubuntu is the Linux distribution that best supports GMA 500, through the use of the ubuntu-mobile. However, the installation procedure is not as simple as other drivers and can lead to many bugs. The Jolicloud has a driver for the GMA500 built in.PixieLive, a GNU/Linux live distribution optimized for GMA500 netbooks can boot from USB Pendrive, SD Card or HardDisk.

What Jolicloud did was that, it integrated the Ubuntu version 8.04 with the Jolicloud kernel and then integrated the Poulsbo DRI with the native kernel DRI alongwith inputting some libraries and packages. Finally Jolicloud was the standard distribution ISO that can support GMA 500 and also the DRI and DRM.

Contributed By : Swagata Nath, Class of 2010, CSE, MIT

Texas Instruments Supports a Wide Range of DSP Devices

Texas Instruments has been active in the DSP space for quite a while and has a wide range of offerings. It has announced the launch of a new microsite catering to DSP related products. I'll urge all our fans here in this community, interested in using DSP devices, to definitely look over the site to get a feel of what's available. That would tell you clearly what's possible to implement with these devices. Why don't review these deices to see if you cannot use it for your final year project!

Diamond could be the key of next generation of supercomputers

Scientists in California are developing diamond-based computers that, they believe, would store millions of times more information than the current silicon-based systems. The researchers have used commercially available technology to pattern large sheets of diamonds with tiny, nitrogen-filled holes. According to scientists, diamond sheets patterned with thousands of nitrogen atoms could provide the basis for a supercomputer. The nitrogen-vacancy diamonds, as the sheets are called by scientists, could store millions of times more information than the silicon-based system and process that information dozens of times faster. Exactly how diamond-based computing would be used has yet to be determined, but applications could range from designing more efficient silicon-based computers to drug development and cryptography. Nitrogen has been in diamonds for as long as there have been diamonds; it's why some diamonds have a yellow hue. For years scientists have used these natural, nitrogen-infused diamonds to study various aspects of quantum mechanics.


Contributed By: Radha Krishna Jana,Faculty, Dept of CSE, MIT