The History Of The SPARC processor

In the history of evolution of the processors, SPARC holds a special place. It was the flagship of Sun Microsystems, then king of the performance servers. Somewhere during the journey it lost its place to the onslaught of the high performance and multicore brigade of Intel/AMD chips. IBM Power was/is a formidable opponent too. Oracle buying up Sun added to the uncertainties.

Besides the version changes and the improvements dealt in the article, what is interesting is that this was a shining example of the RISC cult that shook the world computing world quite a bit. RISC philosophy talks about 80% of the computation work being done by about 20% of the instructions of any computer system. So, the proponents advocated simplifying the ISA of processors. Just the raw available power available with the CISC processors are so much that this efficiency debate has gone away. That Sparc was an important mileston.er of the silicon pro.ecressor evolution history, that it held an important place for 20 odd years, is undeniable.

The History Of The SPARC processor « UNIX

Are 4 bit processors in use still?!

One would think the 4 bitters are dead by now! Not so! They survive and they do so in some interesting ways. Read the complete article below for details, Robert Carvotta has done a wonderful coverage in his article. But here are the highlights.

1. There are quite a few manufacturers still selling 4 bit devices. These are Atmel, EM Microelectronics, and Epson as well as NEC Electronics, Renesas, Samsung, and National. 

2. Some are continuing their lines to support legacy applications, that is not very surprising. Atmel and EM Microelectronic among them. EM chips appear to be present in timepiece designs largely.

3.These go into high volume products such as the Gillette Fusion proGlide.

4. EM Electonics sells them as ROM based devices, developers use them as another hard configured device, not programmable at all.

5. As many of these devices can work with 0.6 V power supply, with low duty cycle applications it can fit into applications where a single battery can serve for the lifetime of the appliance. Applications where the device is possibly sleeping 90% of the time.

6. What else could be responsible for letting these devices survive so long!!

Considerations for 4-bit processing

iPad 2 likely to have dual core chip

Ashok Kumar an analyst at a full service investment bank Rodman & Renshaw foresees Apple upgrading iPad as well as iPhone to dual core processors. he expects this upgrade to be to a pair of 1GHz ARM Cortex A9 cores.  he sees these upgrades coming in Mar for the iPad  and by late summer for the iPhone. The timing may be in question but, the fact that a upgrade is required to compete with  devices like RIM playbook and the Motorola tablet is a given.

Analyst: iPad 2 to sport dual-core chip

Power Architecture and Energy Management

The latest version of the ISA specifications for the Power architecture, Power ISA v.2.06 published Feb last year, introduces mechanisms in the architecture that help power management in chips based on the spec. Besides decreasing the energy demand in general, processors to be used in embedded applications need power management such that things can be done at as low a power demand as possible. Overall architecture has to take the low consumption into account and layouts made accordingly, of course.


Most these sophisticated chips use dynamic circuitry that draw more power as the clock speed goes up. So, sections of hardware circuitry that are not needed during a particular use, can have clock to these sections choked off. This is a well known technique and is being introduced in processor chips for some time. This specification also introduces  "clock gating" as a tool to manage power. Overall the core frequency can be manipulated to manage consumption. For example, it can be pushed up when the processor has to handle heavy processing load, while it can be reduced in other situations. Software can dynamically increase or decrease the core’s clock frequency while the rest of the system keeps operating at an earlier value.


The Power ISA v.2.06 allows for power management on hypervisor and virtualization on single and multi-core processor implementations. A dynamic energy management lets parts of the core to operate and other parts not required to be power gated. For example execution units in the processor pipeline could be power-gated when idle. The architecture offers software-selectable power-saving modes. These modes may reduce the functionality in some areas, such as limiting cache and bus-snooping operations. In some operation scenarios you may turn off all functional units except for interrupts. This architecture now also enables execution of an instruction that can shut off the chip and let it wake up only on an external event.  read the following article for further details.

Energy Management in Power Architecture

Oracle to halve core count in next Sparc processor

Would you believe this! Oracle, who owns Sun now wants a less powerful, less number of cores on their latest Sparc version. The Sparc T3 had graduated to 16 cores, but now they have announced that the next Sparc T4 will have only 8 cores! All you budding computer scientists, try and figure out why! Read the article. I may even do a post summarizing the reason!

Oracle to halve core count in next Sparc processor | Hardware - InfoWorld

NEON Technology (Advanced SIMD)

NEON technology in nothing but an advance version of SIMD (single instruction multiple data ). 64-bit and 128-bit SIMD instructions are combined together to increase performance in standardized application of media and signal processing. NEON can execute MP3 audio decoding on CPUs running at 10 MHz and can run the GSM  AMR (Adaptive Multi-Rate) speech codec at no more than 13 MHz. Different sized data type and operators such as 8-, 16-, 32- and 64-bit integer and single-precision (32-bit) floating-point data are supported by NEON technology. Those data and operations are very efficient to handle audio and video processing as well as graphics and gaming processing. The NEON hardware shares the same floating-point registers as used in Vector Floating Point. In NEON, the SIMD supports up to 16 operations at the same time.




Contributed by: Amalendu Si, IT department