About the Processor in your pocket

Do you know who is working inside your mobile ?

It is ARM.

ARM processors are used in nearly every mobile phone and every PDA made.There are lots of them in every car, running systems like airbags, fuel injection and ABS, in fact they are embedded in most of the world’s electronic devices.. Professor Stephen Furber is the principal designer of the ARM 32 bit RISC microprocessor, found in most handheld electronic devices and in more than 98 % of the world’s mobile phones. The development of the fast, energy efficient 32 bit processor 25 years ago unlocked the world of consumer electronics and to date, more than 18 billion ARM-based chips have been manufactured.

The ARM is a 32-bit reduced instruction set computer (RISC) instruction set architecture (ISA) developed by ARM Holdings. It was known as the Advanced RISC Machine, and before

that as the Acorn RISC Machine. RISC stands for Reduced Instruction Set Computer. If the number of different instructions that a microprocessor can execute is reduced then it can execute them more quickly. This can be a big difference as each instruction takes less clock cycles (mainly just one cycle with the ARM). Also the processor will be a lot simpler, so will be cheaper to make and use less power

The ARM architecture includes the following RISC features:

• Uniform 16 × 32-bit register file.
• Load / store architecture.
• No support for misaligned memory accesses (now supported in ARMv6 cores, with some exceptions related to load/store multiple word instructions).
• Fixed instruction width of 32 bits to ease decoding and pipelining, at the cost of decreased code density. Later, "Thumb mode" increased code density.
• Mostly single-cycle execution.

To compensate for the simpler design, compared with contemporary processors like the Intel 80286 and Motorola 68020, some additional design features were used:

• Conditional execution of most instructions, reducing branch overhead and compensating for the lack of a branch predictor.
• Arithmetic instructions alter condition codes only when desired.
• 32-bit barrel shifter which can be used without performance penalty with most arithmetic instructions and address calculations.
• Powerful indexed addressing modes.
• A link register for fast leaf function calls.
• Simple, but fast, 2-priority-level interrupt subsystem with switched register banks.

Pipelines and other implementation issues

The ARM7 and earlier implementations have a three stage pipeline. The stages are fetch, decode, and execute. Higher performance designs, such as the ARM9, have deeper pipelines: Cortex-A8 has thirteen stages

The architecture provides a non-intrusive way of extending the instruction set using "coprocessors" which can be addressed using MCR, MRC, MRRC, MCRR, and similar instructions.